Search - ip core

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

Description: xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
Platform: | Size: 1432576 | Author: ningchang | Hits:

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473088 | Author: Jack | Hits:

[File Format] ip-core-verification-based-on-vhdl

Description: 在万方数据库中载的，有参考价值，自然科学基金支持项目-in popular database contains the reference value, the Natural Science Fund to support projects
Platform: | Size: 379904 | Author: 王嘉 | Hits:

[VHDL-FPGA-Verilog] mlite.tar

Description: Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
Platform: | Size: 100352 | Author: xinyang | Hits:

[VHDL-FPGA-Verilog] MIT_MIPS_Core.tar

Description: 麻省理工的一个实验室实现的MIPS IP CORE，可以在FPGA上跑通 -a Massachusetts Institute of Technology laboratory achieved MIPS IP CORE, the FPGA can run on Link
Platform: | Size: 28672 | Author: xinyang | Hits:

[VHDL-FPGA-Verilog] mc8051-VHDL

Description: VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
Platform: | Size: 614400 | Author: 陈同 | Hits:

[Other Embeded program] ps2_keyboard

Description: 这是一个使用ps2 ip core的范例，读取键盘输入并显示-This is a used ps2 ip core example, to read keyboard input and display
Platform: | Size: 147456 | Author: HuFengzhang | Hits:

[Other Embeded program] DW8051_2

Description: DW8051 高速8051 IP Core, 本人測試過完全100％正常.-DW8051 High-Speed 8051 IP Core, I tested 100 percent completely normal.
Platform: | Size: 67584 | Author: eddche | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[VHDL-FPGA-Verilog] ml505_pcie_x1_plus

Description: Xilinx 公司PCI Express IP核应用参考设计。通过这个样例，用户可以掌握PCI Express应用设计的一般方法，了解PCI Express的工作原理。-Xilinx Inc. PCI Express IP core reference design applications. Through this example, the user can master the application of the design of PCI Express general approach to understand the working principle of PCI Express.
Platform: | Size: 1798144 | Author: daniel J | Hits:

[VHDL-FPGA-Verilog] core_arm.tar

Description: ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 666624 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] keyboardcontroller.tar

Description: 键盘控制电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-Keyboard control circuit IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 5120 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 88064 | Author: 周华茂 | Hits:

[SCM] LCD_Controller_Altera_MAX_II_CPLD

Description: 基于MAXII CPLD的对1602字符型液晶进行读写操作，其中使用了一个CFI的IP核-MAXII CPLD-based character LCD on the 1602 to read and write operation, which uses a CFI of the IP core
Platform: | Size: 7168 | Author: jaylee | Hits:

[VHDL-FPGA-Verilog] Ethernet_verilog_ip_core

Description: Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。-Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful.
Platform: | Size: 903168 | Author: houlongting | Hits:

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